Computer aided logic design of integrated circuits includes modeling tools that simulate a logic design characterized as an RTL behavioral model, schematic capture tools that convert the logic structure in an RTL behavioral model into layout information, and floor planning/block routing tools that use the layout information to generate semiconductor fabrication information.
Without limiting the scope of the invention, this background information is provided in the context of a specific problem to which the invention has application: making the process of converting the logic structure of an RTL behavioral model M into layout information L (MtoL) more efficient by replacing semi-automated schematic capture tools with an automated MtoL tool. Automating the MtoL process would facilitate the use of what-if analysis to optimize the integrated circuit design.
RTL (register transfer level) behavioral models are generated in the initial stages of computer aided logic design to represent the logic structure and functionality of an integrated circuit. The RTL behavioral model is input to a modeling tool, which simulates the operation of the integrated circuit based on the functionality assigned to the various logic blocks.
The RTL behavioral model, which is written in a modeling language appropriate for the modeling tool, is built in the configuration of an executable hierarchical RTL module tree including software RTL modules that define logic blocks, together with the associated functionality that characterizes the operation of those blocks. The logic structure represented by the model is hierarchical down to the layout style block level, designated leaf nodes, so that the model takes the form of an hierarchical module tree including leaf nodes at the lowest level of the hierarchy.
Thus, an integrated circuit may include a CPU that includes an ALU and a CLU, each of which is made up of two standard layout style logic blocks: data path and standard cell. The layout style blocks are characterized by standard gate-level logic cells which form the basic logic building blocks for the integrated circuit design.
Block routing tools generate semiconductor fabrication information that can be used to generate photolithographic masks and to control etching layout operations. The block router processes layout information in the form of a set of bounding boxes (including geometry, terminal location, and placement) and an associated terminal interconnect netlist. A floor planner tool may be used as a graphical preprocessor to the block router for optimizing block placement, size, and aspect ratio.
Schematic capture tools are used in converting the RTL behavioral modes--specifically, the RTL modules that represent the hierarchical logic block structure--into layout information for input to the block router (or floor planner). However, while schematic capture tools automate the generation of layout information, they do not operate directly on the RTL behavioral model. Rather, a trained user must convert RTL modules into an intermediate set of schematic icons.
Schematic capture tools are disadvantageous in a number of respects. Because the conversion of RTL modules (logic blocks) into schematic icons is not automated, this process is time consuming and susceptible to errors. To achieve any significant level of efficiency for this process requires a substantial investment in training. Moreover, the effort involved in generating an icon set makes impractical any significant amount of iterative what-if analysis of the logic design.
Accordingly, a need exists for an automated MtoL tool to convert an RTL behavioral model the layout information that can be input to a block router (or floor planner) for generating semiconductor fabrication information.